Real-Time Stereo Vision Processing System in a FPGA

@article{Cuadrado2006RealTimeSV,
  title={Real-Time Stereo Vision Processing System in a FPGA},
  author={Carlos Cuadrado and Aitzol Zuloaga and J. L. Martin and Jes{\'u}s L{\'a}zaro and Jaime Jimenez},
  journal={IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics},
  year={2006},
  pages={3455-3460}
}
This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. The configurable description of a stereo processor provides the entity to design stereo matching systems, implementing by incremental design multi-baseline or multi-scale stereo… CONTINUE READING
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