Real-Time Communication for Multicore Systems with Multi-domain Ring Buses

Abstract

We address the problem of scheduling real-time data transactions on a multicore processor bus. In particular, to in-crease system predictability and tighten WCET estimation, we propose to employ a software-controllable Multi-Domain Ring Bus (MDRB) architecture. The problem of scheduling periodic real-time transactions on MDRB is challenging because the bus… (More)
DOI: 10.1109/RTCSA.2010.32

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