Reactive Multi-word Synchronization for Multiprocessors

  title={Reactive Multi-word Synchronization for Multiprocessors},
  author={Phuong Hoai Ha and Philippas Tsigas},
  booktitle={J. Instruction-Level Parallelism},
Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hardware primitives such as compare-and-swap, load-linked/store-conditional and fetch-and-op, from which the higher-level synchronization operations are then implemented in software. Although the single-word hardware primitives are conceptually powerful enough to support higher-level synchronization, from the programmer's… CONTINUE READING


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