Re-synthesis for delay variation tolerance

  title={Re-synthesis for delay variation tolerance},
  author={Shih-Chieh Chang and Cheng-Tao Hsieh and Kai-Chiang Wu},
  journal={Proceedings. 41st Design Automation Conference, 2004.},
Several factors such as process variation, noises, and delay defects can degrade the reliabilities of a circuit. Traditional methods add a pessimistic timing margin to resolve delay variation problems. In this paper, instead of sacrificing the performance, we propose a re-synthesis technique which adds redundant logics to protect the performance. Because nodes in the critical paths have zero slacks and are vulnerable to delay variation, we formulate the problem of tolerating delay variation to… CONTINUE READING