Range and bitmask analysis for hardware optimization in high-level synthesis
High-level synthesis tools are increasingly adopted for designing complex applications on FPGAs. These tools necessitate fast and accurate estimation of FPGA resources in order to produce good design solutions while minimizing design time. Multiplication operations are very commonly found in signal processing, communication, video and image processing applications. In this paper, we present a rapid technique to estimate DSPs utilization for different types of multiplication operations during high-level synthesis. The proposed technique models the synthesis inferences and optimizations performed by state-of-the-art FPGA design tool in order to reliably estimate the number of DSPs and associated LUTs cost of multiplication operations.