Random charge effects for PMOS NBTI in ultra-small gate area devices

@article{Agostinelli2005RandomCE,
  title={Random charge effects for PMOS NBTI in ultra-small gate area devices},
  author={M. Agostinelli and S. Pae and W. K. Yang and C. Prasad and D. L. Kencke and S. Ramey and Eric Snyder and Sandeep Kashyap and Marshall Jones},
  journal={2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.},
  year={2005},
  pages={529-532}
}
PMOS transistor degradation due to negative bias temperature instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper… CONTINUE READING
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