Random Adjacent Sequences: An Efficient Solution for Logic BIST

Abstract

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness of universal test sequences produced by such a generation technique in detecting stuck-at, path delay and bridging faults, we demonstrate that using RSIC generation is one of the best and most practical way to reach a high level of defect coverage during BIST of digital circuits.

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@inproceedings{David2001RandomAS, title={Random Adjacent Sequences: An Efficient Solution for Logic BIST}, author={Ren{\'e} David and Patrick Girard and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel}, booktitle={VLSI-SOC}, year={2001} }