Design of the coarse-grained reconfigurable architecture DART with on-line error detection
This letter presents the design and evaluation of a coarse grained reconfigurable array, hardened against radiation induced transient errors. The architecture consists of an 8 × 8 array of reconfigurable cells, each provided with a built-in soft error detection and instruction roll-back control. We also present the communication management scheme between the processors in the presence of varying degrees of single event upsets. The impact on throughput while evaluating an 8 × 8 discrete wavelet transform (DWT) and 8 × 8 discrete cosine transform (DCT) are also presented.