Corpus ID: 60100088

RaPiD-AES: Developing an Encryption-Specific FPGA Architecture

  title={RaPiD-AES: Developing an Encryption-Specific FPGA Architecture},
  author={Ken Eguro},
RaPiD-AES: Developing Encryption-Specific FPGA Architectures 
6 Citations
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications
Issues and approaches to coarse-grain reconfigurable architecture development
  • Ken Eguro, S. Hauck
  • Computer Science
  • 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003.
  • 2003
Resource allocation for coarse-grain FPGA development
  • Ken Eguro, S. Hauck
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2005
Automatic Design of Area-Efficient Configurable ASIC Cores
Survey on Coarse Grained Reconfigurable Architectures
Domain-Specific Reconfigurable PAL / PLA Creation for SoC


DES key breaking, encryption and decryption on the XC6216
  • T. Kean, Ann Duncan
  • Computer Science
  • Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)
  • 1998
The CAST-256 Encryption Algorithm
Decorrelated Fast Cipher: an AES Candidate
The FPGA implementation of the RC6 and CAST-256 encryption algorithms
  • M. Riaz, H. Heys
  • Computer Science
  • Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411)
  • 1999
Realization of the Round 2 AES Candidates using Altera FPGA
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
High Speed FPGA Architectures for the Data Encryption Standard
Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine
Lucifer, a Cryptographic Algorithm