RTL level implementation of high speed-low power Viterbi Encoder & Decoder

@article{Singh2013RTLLI,
  title={RTL level implementation of high speed-low power Viterbi Encoder & Decoder},
  author={Pooran Singh and S. K. Vishvakarma},
  journal={2013 IEEE Third International Conference on Information Science and Technology (ICIST)},
  year={2013},
  pages={345-349}
}
High speed and low power Viterbi Encoder Decoder of rate ½ convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi encoder-decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it's functioning on 393.544 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-10 of 12 references

A Low-Power Radix-4 Viterbi Decoder Based on DCVSPG Pulsed Latch with Sharing Technique

  • Xin-Ru Lee
  • IEEE Asia Pacific conference on Circuits…
  • 2010
1 Excerpt

An Efficient Metric Normalization Architecture for High-speed Low- power Viterbi Decoder

  • Kelvin Yi-Tse Lai
  • TENCON-2007, IEEE Region Ten Conference. 349
  • 2007

Memory management in traceback Viterbi decoders

  • O. Collins, F. Pollara.
  • TDA Prog. Rep, pages 42–99, 1989.
  • 1989

Similar Papers

Loading similar papers…