RTL level implementation of high speed-low power Viterbi Encoder & Decoder

  title={RTL level implementation of high speed-low power Viterbi Encoder & Decoder},
  author={Pooran Singh and S. K. Vishvakarma},
  journal={2013 IEEE Third International Conference on Information Science and Technology (ICIST)},
High speed and low power Viterbi Encoder Decoder of rate ½ convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi encoder-decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it's functioning on 393.544 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one… CONTINUE READING


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