RT-level TPG Exploiting High-Level Synthesis Information


High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to Genetic… (More)
DOI: 10.1109/VTEST.1999.766685


6 Figures and Tables


Citations per Year

Citation Velocity: 7

Averaging 7 citations per year over the last 3 years.

Learn more about how we calculate this metric in our FAQ.

Cite this paper

@inproceedings{Chiusano1999RTlevelTE, title={RT-level TPG Exploiting High-Level Synthesis Information}, author={Silvia Chiusano and Fulvio Corno and Paolo Prinetto}, booktitle={VTS}, year={1999} }