RT-Bench: an Extensible Benchmark Framework for the Analysis and Management of Real-Time Applications

@article{Nicolella2022RTBenchAE,
  title={RT-Bench: an Extensible Benchmark Framework for the Analysis and Management of Real-Time Applications},
  author={Mattia Nicolella and Shahin Roozkhosh and Denis Hoornaert and Andrea Bastoni and Renato Mancuso},
  journal={Proceedings of the 30th International Conference on Real-Time Networks and Systems},
  year={2022}
}
Benchmarking is crucial for testing and validating any system, including—and perhaps especially—real-time systems. Typical real-time applications adhere to well-understood abstractions: they exhibit a periodic behavior, operate on a well-defined working set, and strive for stable response time, avoiding non-predicable factors such as page faults. Unfortunately, available benchmark suites fail to reflect key characteristics of real-time applications. Practitioners and researchers must resort to… 

References

SHOWING 1-10 OF 38 REFERENCES
Splash-3: A properly synchronized benchmark suite for contemporary research
TLDR
This work analyzes the Splash-2 benchmarks and exposes critical performance bugs that may question some of the reported benchmark results, and contributes to the community a new sanitized version of the Splash -3 benchmark suite.
Governing with Insights: Towards Profile-Driven Cache Management of Black-Box Applications
TLDR
This paper describes a novel methodology, namely Black-Box Profiling (BBProf), to gather fine-grained insights on the usage of cache resources in applications of realistic complexity and provides an open-source full-system implementation and showcases how BBProf can be used to perform profile-driven cache management.
Dissecting the CUDA scheduling hierarchy: a Performance and Predictability Perspective
TLDR
This paper corrects and consolidates previously published assumptions about the hierarchical scheduling policies of NVIDIA GPUs and their proprietary CUDA application programming interface and discusses how such mechanisms evolved with recently released GPU micro-architectures, and how such changes influence the scheduling models to be exploited by real-time system engineers.
TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research
TLDR
Open-source programs are collected, adapted to a common coding style, and provided in open-source, with the main features of TACLeBench, which is that all programs are self-contained without any dependencies on standard libraries or an operating system.
The Potential of Programmable Logic in the Middle: Cache Bleaching
TLDR
It is demonstrated that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory, and the approach is leveraged to solve long-standing issues with cache coloring.
Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems
TLDR
It is shown that cache partitioning does not necessarily ensure predictable cache performance in modern COTS multicore platforms that use non-blocking caches to exploit memory- level-parallelism (MLP), and a hardware and system software collaborative approach is proposed to efficiently eliminate MSHR contention for multicore real-time systems.
Analysis of Memory-Contention in Heterogeneous COTS MPSoCs
TLDR
A framework to analyze the memory contention in COTS MPSoCs and provide safe and tight bounds to the delays suffered by any critical task due to this contention is proposed and comparisons with the state-of-the art approaches show that the proposed analysis provides the tightest bounds across all evaluated access scenarios.
Improving the Accuracy of Cache-Aware Response Time Analysis Using Preemption Partitioning
Schedulability analyses for preemptive real-time systems need to take into account cache-related preemption delays (CRPD) caused by preemptions between the tasks. The estimation of the CRPD values
Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems
TLDR
A novel method of studying cache contents and their evolution via snapshotting is explored, which complements extant approaches for cache profiling to better formulate, validate, and refine hypotheses on the behavior of modern caches.
Attack Detection Through Monitoring of Timing Deviations in Embedded Real-Time Systems
TLDR
This paper presents a technique to detect attacks in RTES based on timing information, designed for single-core processors, based on a monitor implemented in hardware to preserve the predictability of instrumented programs.
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