RISC I: a reduced instruction set VLSI computer

  title={RISC I: a reduced instruction set VLSI computer},
  author={David A. Patterson and Carlo H. S{\'e}quin},
  booktitle={International Symposium on Computer Architecture},
The Reduced Instruction Set Computer (RISC) Project investigates an alternative to the general trend toward computers with increasingly complex instruction sets: With a proper set of instructions and a corresponding architectural design, a machine with a high effective throughput can be achieved. [] Key Method Overlapping sets of register banks that can pass parameters directly to subroutines are largely responsible for the excellent performance of RISC I. Static and dynamic comparisons between this new…

Comparative Study of RISC Architectures

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Design of the RISC-V Instruction Set Architecture

This dissertation presents the RISC-V instruction set architecture, a free and open ISA that builds and improves upon the original Reduced Instruction Set Computer (RISC) architectures, structured as a small base ISA with a variety of optional extensions.

An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

This work develops mathematical performance models of three conventional microprocessor designs, and proposes a symmetry-improving nonlinear optimization method to achieve code-to-design mapping, which suggests that codes accumulating as low as 5% hazard causing instructions execute more swiftly on processors without pipelines.

Reduced Instruction Set Architecture for a GaAs Microprocessor System

Gate densities that permit the integration of an entire microprocessor on a single chip have been reached in GaAs technology and the streamlined architecture minimizes latencies between instructions while allowing for parallel operation between the CPU and the FCOP.

High performance issue oriented architecture

The reduced instruction parallel/pipelined (RIP) architecture was designed as a robust architecture to meet a wide range of system requirements across a family of implementations.

Central Processing Unit

  • A. Bindal
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    Fundamentals of Computer Architecture and Design
  • 2019
This chapter is all about the design of a simple Reduced Instruction Set Computer (RISC) for central processing, and the operation of various cache architectures, cache read-and-write protocols, functionality of write-through and write-back caches.

Leros: the Return of the Accumulator Machine

The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.

Instruction-level parallel processing: History, overview, and perspective

An overview and historical perspective of the field of ILP and its development over the past three decades is provided.

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  • Computer Science
As the complexity of processors increased, superpipelined superscalar processors evolved while striving to increase and exploit the amount of ILP available in code and architecture.

An Analisys of Dynamic Instruction Usage with 32 Bit MIPS, PowerPC and SPARC Processors on Embedded Applications

A comparison of the instruction set usage of the 32 bits microprocessors MIPS, PowerPC and SPARC is presented and the effects of three levels of optimization on dynamic instructions are assessed and small differences in instruction counts are found.



The case for the reduced instruction set computer

It is argued that the next generation of VLSI computers may be more effectively implemented as RISC's than CISC's, and in fact may even do more harm than good.

How to Use 1000 Registers

A spectrum of ways to exploit more registers in an architecture is discussed, ranging from programmer-managed cache (large numbers of explicitly-addressed registers, as in the Cray-1) to better schemes for automatically- managed cache.

Design Considerations for Single-Chip Computers of the Future

It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip.

Design considerations for the VLSI processor of X-TREE

X-NODE is a single-chip VLSI processor to be realized in the mid 1980's and to be used as a building block for a tree-structured multiprocessor system (X-TREE). Three major trends influence the

Static and Dynamic Characteristics of XPL Programs

The main interest is in the discovery of primitive operations, implied by the semantics of a programming language, that can be added to the firmware or hardware of a computer to improve overall system performance.

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It is found that a high-level structured language such as Pascal provides unique opportunities for effective optimization, but that standard optimization techniques must be extended to take advantage of these opportunities.

A portable compiler: theory and practice

An overview of the compiler structure and algorithms is given, emphasizing those areas where theory was helpful, and discussing the approaches taken where theory is lacking.

Retrospective on high-level language computer architecture

The intent of this paper is to identify and discuss several issues applicable to high-level language computer architecture, to provide a more concrete definition of high- level language computers, and to suggest a direction for high-levels language computer architectures of the future.

VAX-11/780 - A virtual address extension to the DEC PDP-11 family

  • W. Strecker
  • Computer Science
    AFIPS National Computer Conference
  • 1978

Dynamic Pascal statistics (in progress

  • Dynamic Pascal statistics (in progress
  • 1980