RISC I: a reduced instruction set VLSI computer

@inproceedings{Patterson1998RISCIA,
  title={RISC I: a reduced instruction set VLSI computer},
  author={David A. Patterson and Carlo H. S{\'e}quin},
  booktitle={International Symposium on Computer Architecture},
  year={1998}
}
The Reduced Instruction Set Computer (RISC) Project investigates an alternative to the general trend toward computers with increasingly complex instruction sets: With a proper set of instructions and a corresponding architectural design, a machine with a high effective throughput can be achieved. [] Key Method Overlapping sets of register banks that can pass parameters directly to subroutines are largely responsible for the excellent performance of RISC I. Static and dynamic comparisons between this new…

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