RISC I: A Reduced Instruction Set VLSI Computer

@inproceedings{Patterson1981RISCIA,
  title={RISC I: A Reduced Instruction Set VLSI Computer},
  author={David A. Patterson and Carlo H. S{\'e}quin},
  booktitle={25 Years ISCA: Retrospectives and Reprints},
  year={1981}
}
The Reduced Instruction Set Computer (RISC) Project investigates an alternatrve to the general trend toward computers wrth increasingly complex instruction sets: With a proper set of instructions and a corresponding architectural design, a machine wrth a high effective throughput can be achieved. The simplicity of the instruction set and addressing modes allows most Instructions to execute in a single machine cycle, and the srmplicity of each instruction guarantees a short cycle time. In… CONTINUE READING

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