RIPL: An Efficient Image Processing DSL for FPGAs

  title={RIPL: An Efficient Image Processing DSL for FPGAs},
  author={Robert J. Stewart and Deepayan Bhowmik and Greg J. Michaelson and Andrew M. Wallace},
  journal={Journal of Functional Programming},
  pages={428 - 429}
Field programmable gate arrays (FPGAs) can accelerate image processing by exploiting finegrained parallelism opportunities in image operations. FPGA language designs are often subsets or extensions of existing languages, though these typically lack suitable hardware computation models so compiling them to FPGAs leads to inefficient designs. Moreover, these languages lack image processing domain specificity. Our solution is RIPL1, an image processing domain specific language (DSL) for FPGAs. It… Expand


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