REGIMap: Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs)

@article{Hamzeh2013REGIMapRA,
  title={REGIMap: Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs)},
  author={Mahdi Hamzeh and Aviral Shrivastava and Sarma B. K. Vrudhula},
  journal={2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)},
  year={2013},
  pages={1-10}
}
Coarse-Grained Reconfigurable Architectures (CGRAs) are an extremely attractive platform when both performance and power efficiency are paramount. [...] Key Result A unique feature of our heuristic is that it learns from failed attempts and constructively changes the schedule to achieve better mappings at lower compilation times.Expand
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THE NATIONAL UNIVERSITY OF SINGAPORE School of Computing
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References

SHOWING 1-10 OF 29 REFERENCES
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures
TLDR
Experiments on a wide variety of compute-intensive loops from the multimedia domain show that EMS improves throughput by 25% over traditional iterative modulo scheduling, and achieves 98% of the throughput of simulated annealing techniques at a fraction of the compilation time. Expand
EPIMap: Using Epimorphism to map applications on CGRAs
TLDR
Experimental results on 14 important kernels extracted from well known benchmark programs show that using EPIMap can improve the performance of the kernels on CGRA by more than 2.8X on average, as compared to one of the best existing mapping algorithm, EMS. Expand
A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures
TLDR
A graph drawing based approach, split-push kernel mapping (SPKM), for mapping applications onto CGRAs, which can map on average 4.5times more applications than the previous approach, while generating mappings which have better qualities in terms of utilized CGRA resources. Expand
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
TLDR
This paper investigates the influence of register file partitions, register file sizes and the interconnection topology of ADRES, and proposes an enhanced architecture instantiation that improves performance by 60 - 70% and reduces energy by 50%. Expand
SPR: an architecture-adaptive CGRA mapping tool
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placementExpand
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
TLDR
The experimental results showed that the operation parallelism was significantly improved by the mapping approach and the relation that exists between the performance improvements and the memory access latency, the interconnection network and the processing elements' register file size. Expand
A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template
TLDR
An efficient modulo scheduling algorithm for a CGRA template with separation of resource reservation and scheduling, use of a compact three-dimensional architecture graph and a resource usage aware relocation algorithm is presented. Expand
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures
TLDR
This paper presents a retargetable compiler for a family of coarse-grained reconfigurable architectures and presents experimental results, showing up to 28.7 instructions per cycle (IPC) over tested kernels. Expand
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources
  • E. Mirsky, A. DeHon
  • Computer Science
  • 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines
  • 1996
TLDR
MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution that can serve as an instruction store, a memory element, or a computational element, and the adaptability is made possible by a multi-level configuration scheme. Expand
PipeRench: a co/processor for streaming multimedia acceleration
TLDR
A novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations, which enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. Expand
...
1
2
3
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