RAMP : A Model for Reliability Aware MicroProcessor Design

@inproceedings{Srinivasan2003RAMPA,
  title={RAMP : A Model for Reliability Aware MicroProcessor Design},
  author={Jayanth Srinivasan and Sarita V. Adve and Pradip Bose and Chao-Kun Hu},
  year={2003}
}
This report introducesRAMP , an architectural model for long-term processor reliabili ty measurement. With aggresive transistor scaling and increasing pro cessor power and temperature, reliability due to wear-out mechanisms is expected to become a significant is sue n microprocessor design. Reliability awareness at the microarchitectural design stage will s oon be a neccessity and RAMP provides a convenient abstraction to do so. RAMP models chip wide mean time to failure as a function of the… CONTINUE READING
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