RAMP : A Model for Reliability Aware MicroProcessor Design

  title={RAMP : A Model for Reliability Aware MicroProcessor Design},
  author={Jayanth Srinivasan and Sarita V. Adve and Pradip Bose and Chao-Kun Hu},
This report introducesRAMP , an architectural model for long-term processor reliabili ty measurement. With aggresive transistor scaling and increasing pro cessor power and temperature, reliability due to wear-out mechanisms is expected to become a significant is sue n microprocessor design. Reliability awareness at the microarchitectural design stage will s oon be a neccessity and RAMP provides a convenient abstraction to do so. RAMP models chip wide mean time to failure as a function of the… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 37 references

Scaling effect on electromigration in on -chip cu wiring

  • C.-K.Hu
  • In International Electron Devices Meeting,
  • 1999
Highly Influential
5 Excerpts

Design of Hig h-Performance Microprocessor Circuits

  • A. Chandrakasan, W. J. Bowhill, F. Fox
  • 2001
Highly Influential
3 Excerpts

Comparison of cu electromigration lifeti me in cu interconnects coated with various caps

  • C-K.Hu
  • In Applied Physics Letters,
  • 2003
1 Excerpt

Exploiting microarchitectural re dundancy for defect tolerance

  • P. Shivakumar
  • In 21st International Conference on Computer…
  • 2003
1 Excerpt

Leakage, breakdown, and tddb characte ristics of porous low-k silica based interconnect materials

  • E.T.Ogawa
  • InInternational Reliability Physics Symposium,
  • 2003
1 Excerpt

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