Corpus ID: 36162411

R16: A New Transputer Design for FPGAs

  title={R16: A New Transputer Design for FPGAs},
  author={John Jakson},
  • John Jakson
  • Published in CPA 2005
  • Computer Science
  • This paper describes the ongoing development of a new FPGA hosted Transputer using a Load Store RISC style Multi Threaded Architecture (MTA). The memory system throughput is emphasized as much as the processor throughput and uses the recently developed Micron 32MByte RLDRAM which can start fully random memory cycles every 3.3ns with 20ns latency when driven by an FPGA controller. The R16 shares an object oriented Memory Manager Unit (MMU) amongst multiple low cost Processor Elements (PEs) until… CONTINUE READING


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