Corpus ID: 36162411

R16: A New Transputer Design for FPGAs

@inproceedings{Jakson2005R16AN,
  title={R16: A New Transputer Design for FPGAs},
  author={John Jakson},
  booktitle={CPA},
  year={2005}
}
  • John Jakson
  • Published in CPA 2005
  • Computer Science
  • This paper describes the ongoing development of a new FPGA hosted Transputer using a Load Store RISC style Multi Threaded Architecture (MTA). The memory system throughput is emphasized as much as the processor throughput and uses the recently developed Micron 32MByte RLDRAM which can start fully random memory cycles every 3.3ns with 20ns latency when driven by an FPGA controller. The R16 shares an object oriented Memory Manager Unit (MMU) amongst multiple low cost Processor Elements (PEs) until… CONTINUE READING
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    References

    SHOWING 1-10 OF 16 REFERENCES
    Legacy of the transputer
    • 10
    • PDF
    Hardware for transputing without transputers
    • 4
    The Verilog® Hardware Description Language
    • 668
    • PDF
    Pentium Processor Optimization Tools
    • 6
    Advanced Computer Arithmetic Design
    • 153
    Computer Architecture: A Quantitative Approach
    • 11,253
    • PDF
    The Art in Computer Programming
    • 6,798
    • PDF
    Algorithms in C
    • 1,040
    • PDF