Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

  title={Quantization noise improvement of Time to Digital converter (TDC) for ADPLL},
  author={Jawaharlal Tangudu and Sarma Gunturi and Saket Jalan and Jayawardan Janardhanan and Raghu Ganesan and Debapriya Sahu and Khurram Waheed and John L. Wallberg and Robert Bogdan Staszewski},
  journal={2009 IEEE International Symposium on Circuits and Systems},
A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒc, based on a input reference frequency ƒref. As part of the phase error measurement of the PLL, a Time to Digital converter(TDC) is used to measure the delay between ƒref clock edge and… CONTINUE READING
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