QED: Quick Error Detection tests for effective post-silicon validation
@article{Hong2010QEDQE,
title={QED: Quick Error Detection tests for effective post-silicon validation},
author={Ted Hong and Yanjing Li and Sung-Boem Park and Diana Mui and David C. Lin and Ziyad Abdel Kaleq and Nagib Hakim and Helia Naeimi and Donald S. Gardner and Subhasish Mitra},
journal={2010 IEEE International Test Conference},
year={2010},
pages={1-10}
}Long error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as a system-level failure, is a major challenge in post-silicon validation of robust systems. [] Key Method QED transformations allow flexible tradeoffs between error detection latency, coverage, and complexity, and can be implemented in software with little or no hardware changes. Results obtained from hardware experiments on quad-core Intel® Core™ i7 hardware platforms and from…
Figures and Tables from this paper
79 Citations
Quick error detection tests with fast runtimes for effective post-silicon validation and debug
- Computer Science2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
- 2015
This work presents a new technique called Fast QED, which improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error Detection latencies compared to software-only QED.
Overcoming post-silicon validation challenges through Quick Error Detection (QED)
- Computer Science2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)
- 2013
An overview of QED is presented and it is presented that QED enables 2- to 4-fold improvement in bug coverage and does not require any hardware modification, making it readily applicable to existing designs.
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection
- Computer ScienceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 2014
Results demonstrate that QED shortens error detection latencies by up to nine orders of magnitude to only a few hundred cycles for most bug scenarios, and enables up to a fourfold increase in bug coverage.
Quick detection of difficult bugs for effective post-silicon validation
- Computer ScienceDAC Design Automation Conference 2012
- 2012
An important feature of this technique is its software-only implementation without any hardware modification, which makes it readily applicable to existing designs and enables 2-fold increase in bug coverage.
Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis principles
- Computer Science2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)
- 2015
The Hybrid Quick Error Detection (H-QED) approach is presented that overcomes post-silicon validation and debug challenges for hardware accelerators by leveraging HLS techniques and incurs less than 2% chip-level area overhead with negligible performance impact.
Accelerating microprocessor silicon validation by exposing ISA diversity
- Computer Science2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
- 2011
A self-checking method that accelerates silicon validation and significantly increases the number of applied random tests to improve bug detection efficiency and reduce time-to-market.
QED post-silicon validation and debug: Frequently asked questions
- Computer Science2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)
- 2014
A brief overview of QED is presented, an acronym for Quick Error Detection, which systematically creates a wide variety of validation tests to quickly detect bugs, not only inside processor cores, but also inside uncore components of multi-core SoCs.
Bug Detection and Localization Using Symbolic Quick Error Detection 1
- Computer Science
- 2018
Symbolic QED is fully automatic, unlike manual techniques in use today that can be extremely time-consuming and expensive; requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs.
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
- Computer ScienceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 2019
H-QED improves error detection latencies by 2–5 orders of magnitude with one cycle latencies in presilicon scenarios and bug coverage threefold higher compared to traditional validation techniques, and uncovered previously unknown bugs in the CHStone benchmark suite.
E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods
- Computer ScienceCAV
- 2017
The results on the OpenSPARC T2, an open-source 500-million-transistor multicore chip design, demonstrate the effectiveness and practicality of E-QED: starting with a failed post-silicon test, in a few hours it can automatically narrow the location of the bug to a handful of candidate flip-flops and obtain the corresponding bug trace.
References
SHOWING 1-10 OF 58 REFERENCES
Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)
- Computer ScienceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 2009
Simulation results on a complex superscalar processor demonstrate that IFRA is effective in accurately localizing electrical bugs with very little impact on overall chip area.
ED4I: Error Detection by Diverse Data and Duplicated Instructions
- Computer ScienceIEEE Trans. Computers
- 2002
It is demonstrated how to choose an optimal value of k for the transformation of ED/sup 4/I, and shows that, for integer programs, the transformation with k = -2 was the most desirable choice in six out of seven benchmark programs the authors simulated.
Reversi: Post-silicon validation system for modern microprocessors
- Computer Science2008 IEEE International Conference on Computer Design
- 2008
The framework, called Reversi, generates random programs in such a way that their correct final state is known at generation time, eliminating the need for architectural simulations, and can speed up post-silicon validation by 20x compared to traditional flows.
Error detection by duplicated instructions in super-scalar processors
- Computer ScienceIEEE Trans. Reliab.
- 2002
EDDI can provide over 98% fault-coverage without any extra hardware for error detection, which is especially useful when designers cannot change the hardware, but they need dependability in the computer system.
BackSpace: Formal Analysis for Post-Silicon Debug
- Computer Science2008 Formal Methods in Computer-Aided Design
- 2008
This work introduces a new paradigm for using formal analysis, augmented with some on-chip hardware support, to automatically compute error traces that lead to an observed buggy state, thereby greatly simplifying the post-silicon debug problem.
Automated Selection of Signals to Observe for Efficient Silicon Debug
- Computer Science2009 27th IEEE VLSI Test Symposium
- 2009
Experimental results indicate that the cycle in which a bug first appears can be more rapidly and precisely found with the proposed approach thereby speeding up the post-silicon debug process.
Complementary use of runtime validation and model checking
- Computer ScienceICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.
- 2005
This paper considers the use of on-chip hardware for detecting bugs using hardware assertions and examines the strengths and weaknesses of runtime validation and how it may be used to complement model checking in a hybrid methodology.
Automated data analysis solutions to silicon debug
- Computer Science2009 Design, Automation & Test in Europe Conference & Exhibition
- 2009
An automated software solution to analyze the data collected during silicon debug to detect suspects in both the spatial and the temporal domain is presented.
Automated Debug of Speed Path Failures Using Functional Tests
- Computer Science2009 27th IEEE VLSI Test Symposium
- 2009
A technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures is presented.
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
- Computer Science26th IEEE VLSI Test Symposium (vts 2008)
- 2008
Experimental results indicate very significant increases in the effective observation window for a trace buffer can be obtained and can rapidly speed up the debug process.














