QED: Quick Error Detection tests for effective post-silicon validation

@article{Hong2010QEDQE,
  title={QED: Quick Error Detection tests for effective post-silicon validation},
  author={Ted Hong and Yanjing Li and Sung-Boem Park and Diana Mui and David C. Lin and Ziyad Abdel Kaleq and Nagib Hakim and Helia Naeimi and Donald S. Gardner and Subhasish Mitra},
  journal={2010 IEEE International Test Conference},
  year={2010},
  pages={1-10}
}
Long error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as a system-level failure, is a major challenge in post-silicon validation of robust systems. [...] Key Method QED transformations allow flexible tradeoffs between error detection latency, coverage, and complexity, and can be implemented in software with little or no hardware changes. Results obtained from hardware experiments on quad-core Intel® Core™ i7 hardware platforms and from…Expand
Quick error detection tests with fast runtimes for effective post-silicon validation and debug
TLDR
This work presents a new technique called Fast QED, which improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error Detection latencies compared to software-only QED. Expand
Quick error detection tests with fast runtimes for effective post-silicon validation and debug
TLDR
This work presents a new technique called Fast QED, which improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error Detection latencies compared to software-only QED. Expand
Overcoming post-silicon validation challenges through Quick Error Detection (QED)
TLDR
An overview of QED is presented and it is presented that QED enables 2- to 4-fold improvement in bug coverage and does not require any hardware modification, making it readily applicable to existing designs. Expand
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection
  • David C. Lin, Ted Hong, +6 authors S. Mitra
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2014
TLDR
Results demonstrate that QED shortens error detection latencies by up to nine orders of magnitude to only a few hundred cycles for most bug scenarios, and enables up to a fourfold increase in bug coverage. Expand
Quick detection of difficult bugs for effective post-silicon validation
TLDR
An important feature of this technique is its software-only implementation without any hardware modification, which makes it readily applicable to existing designs and enables 2-fold increase in bug coverage. Expand
Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis principles
TLDR
The Hybrid Quick Error Detection (H-QED) approach is presented that overcomes post-silicon validation and debug challenges for hardware accelerators by leveraging HLS techniques and incurs less than 2% chip-level area overhead with negligible performance impact. Expand
Accelerating microprocessor silicon validation by exposing ISA diversity
TLDR
A self-checking method that accelerates silicon validation and significantly increases the number of applied random tests to improve bug detection efficiency and reduce time-to-market. Expand
QED post-silicon validation and debug: Frequently asked questions
  • David C. Lin, S. Mitra
  • Computer Science, Engineering
  • 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)
  • 2014
TLDR
A brief overview of QED is presented, an acronym for Quick Error Detection, which systematically creates a wide variety of validation tests to quickly detect bugs, not only inside processor cores, but also inside uncore components of multi-core SoCs. Expand
Bug Detection and Localization Using Symbolic Quick Error Detection 1
We present Symbolic Quick Error Detection (Symbolic QED), a structured approach for logic bug detection and localization which can be used both during pre-silicon design verification as well asExpand
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
  • K. Campbell, D. Lin, +5 authors Deming Chen
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2019
TLDR
H-QED improves error detection latencies by 2–5 orders of magnitude with one cycle latencies in presilicon scenarios and bug coverage threefold higher compared to traditional validation techniques, and uncovered previously unknown bugs in the CHStone benchmark suite. Expand
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