Pyhsical Design Exploration of 3D Tree-based FPGA Architecture

Abstract

An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a mult-dimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silicon Via (TSVs) using a horizontal break-point to re-distribute the Tree interconnects into multiple stacked active silicon layers proposed in this paper.

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Cite this paper

@inproceedings{Pangracious2013PyhsicalDE, title={Pyhsical Design Exploration of 3D Tree-based FPGA Architecture}, author={Vinod Pangracious and Emna Amouri and Habib Mehrez and Zied Marrakchi}, year={2013} }