Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs

@inproceedings{Rebeiro2012PushingTL,
  title={Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs},
  author={Chester Rebeiro and Sujoy Sinha Roy and Debdeep Mukhopadhyay},
  booktitle={CHES},
  year={2012}
}
In this paper we present an FPGA implementation of a highspeed elliptic curve scalar multiplier for binary finite fields. High speeds are achieved by boosting the operating clock frequency while at the same time reducing the number of clock cycles required to do a scalar multiplication. To increase clock frequency, the design uses optimized implementations of the underlying field primitives and a mathematically analyzed pipeline design. To reduce clock cycles, a new scheduling scheme is… CONTINUE READING
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