Pulser gating: A clock gating of pulsed-latch circuits

@article{Kim2011PulserGA,
  title={Pulser gating: A clock gating of pulsed-latch circuits},
  author={Sangmin Kim and Inhak Han and Seungwhun Paik and Youngsoo Shin},
  journal={16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)},
  year={2011},
  pages={190-195}
}
A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with location of latches, we first extract the gating function of each latch; the gating functions are merged to reduce the amount of extra logic… CONTINUE READING
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