Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour

@inproceedings{Madre1988ProvingCC,
  title={Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour},
  author={Jean Christophe Madre and Jean-Paul Billon},
  booktitle={DAC},
  year={1988}
}
This paper presents a new method for verifying functionality in the design of VLSI circuits. Our method fits naturally in a methodology based on a Hardware Description Language (HDL). Two programs describe the system under design: (1) its specification and (2) the extracted behaviour from its layout. Verifying the design comes down to proving that these programs are correct and equivalent with regard to the HDL semantics. We define a process named Formal Analysis that permits to prove these… CONTINUE READING
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