• Corpus ID: 15061967

Proposal For Neuromorphic Hardware Using Spin Devices

@article{Sharad2012ProposalFN,
  title={Proposal For Neuromorphic Hardware Using Spin Devices},
  author={Mrigank Sharad and Charles Augustine and Georgios Panagopoulos and Kaushik Roy},
  journal={ArXiv},
  year={2012},
  volume={abs/1206.3227}
}
We present a design-scheme for ultra-low power neuromorphic hardware using emerging spin-devices. We propose device models for 'neuron', based on lateral spin valves and domain wall magnets that can operate at ultra-low terminal voltage of ~20 mV, resulting in small computation energy. Magnetic tunnel junctions are employed for interfacing the spin-neurons with charge-based devices like CMOS, for large-scale networks. Device-circuit co-simulation-framework is used for simulating such hybrid… 
View PDF on arXiv
43 Citations
Background Citations
11
Methods Citations
5

43 Citations

Citation Type

Citation Type

Boolean and non-Boolean computation with spin devices
TLDR
Device circuit co-design for different classes of neuromorphic architectures using spin-torque based neuron models along with DWM or other memristive synapses show that the spin-based neuromorphic designs can achieve 15X-100X lower computation energy for applications like, image processing, data-conversion, cognitive-computing, pattern matching and programmable-logic, as compared to state of art CMOS designs.
Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices
While the promise of spin-torque devices for future on-chip memory is now well recognized, application of spin devices in computational hardware remains an exploratory research-domain. Several…
A comprehensive compact model for the design of all-spin-logic based circuits
A Mini Review of Neuromorphic Architectures and Implementations
TLDR
This mini review is intended for a general engineering audience not currently familiar with neuromorphic research, and provides descriptions of some of the recent advances, including supercomputer and single-device implementations, approaches based on spiking and nonspiking neurons, machine learning hardware accelerators, and those utilizing memristive devices.
A brain-plausible neuromorphic on-the-fly learning system implemented with magnetic domain wall analog memristors
TLDR
Simulations show that the MAM-boosted neuromorphic system can achieve persistence, can demonstrate deterministic fast on-the-fly learning with the potential for reduced circuitry complexity, and can provide increased capabilities over an all-CMOS implementation.
Designing Neuromorphic Computing Systems with Memristor Devices
TLDR
This dissertation introduces a novel neuromorphic computing for real-time cardiac arrhythmia classification and introduces a preliminary neuromorphic system implementing a deep Generative Adversarial Network (GAN), based on ESNs.
Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives
TLDR
The possibility of applying emerging spin-torque switches in the design of energy-efficient global interconnects, for future chip multiprocessors is discussed.
Ultra low power associative computing with spin neurons and resistive crossbar memory
TLDR
This work presents the design of analog associative memory for face recognition using RCM, where, substituting conventional analog circuits with spin-neurons can achieve ~100× lower power, which makes the proposed design ~1000× more energy-efficient than a 45nm-CMOS digital ASIC, thereby significantly enhancing the prospects of RCM based computational hardware.
Exploring Boolean and non-Boolean computing with spin torque devices
TLDR
The possibility of applying emerging spin-torque switches in the design of energy-efficient global interconnects, for future chip multiprocessors is discussed.
Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing
TLDR
A Magnetic Tunneling Junction (MTJ) has been proposed to perform the thresholding operation of a biological neuron to suggest the possibility of 1.63 - 1.79x power savings in comparison to a 45nm digital CMOS implementation.
...
...

References

SHOWING 1-10 OF 24 REFERENCES
Spin neuron for ultra low power computational hardware
TLDR
Results based on device-circuit co-simulation framework show that a spin-CMOS hybrid design, employing the proposed neuron, can achieve ~100x lower energy consumption per computation-frame, as compared to the state of art CMOS designs employing conventional analog circuits.
Spin based neuron-synapse module for ultra low power programmable computational networks
TLDR
A spin-CMOS hybrid design for neural network using spin torque switched nano-magnets for realizing ultra low power, high speed neuron and domain wall magnets for compact, programmable synapses achieves high integration.
Spin-Based Neuron Model With Domain-Wall Magnets as Synapse
We present artificial neural network design using spin devices that achieves ultralow voltage operation, low power consumption, high speed, and high integration density. We employ spin torque…
Low-power functionality enhanced computation architecture using spin-based devices
TLDR
This paper develops a Functionality Enhanced All Spin Logic (FEASL) architecture and a synthesis framework using Logically Passively Self Dual (LPSD) formulation and synthesized Discrete Cosine Transform (DCT) algorithm using adders and multipliers to show the efficacy of the proposed FEASL approach in designing digital signal processing (DSP) systems.
Ultra low energy analog image processing using spin based neurons
TLDR
Results indicate that the proposed design scheme can achieve more than two orders of magnitude reduction in computation energy, as compared to the state of art CMOS designs, that are based on conventional mixed-signal image acquisition and processing schemes.
Proposal for an all-spin logic device with built-in memory.
TLDR
This work proposes a spintronic device that uses spin at every stage of its operation and shows the five essential characteristics for logic applications: concatenability, nonlinearity, feedback elimination, gain and a complete set of Boolean operations.
Cognitive computing with spin-based neural networks
TLDR
Simulations for cognitive as well as Boolean computation applications show more than 94% improvement in power consumption as compared to a conventional CMOS design at the same technology node.
True Energy-Performance Analysis of the MTJ-Based Logic-in-Memory Architecture (1-Bit Full Adder)
The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based…
Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions
Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay.…
Low Energy Magnetic Domain Wall Logic in Short, Narrow, Ferromagnetic Wires
TLDR
Circuit simulation results of an implementation of universal logic that operates at low switching energy are presented, showing that the magnetic logic gates can operate at lower switching energy than CMOS electronics.
...
...