Proof of correctness of high-performance 3-1 interlock collapsing ALUs

  title={Proof of correctness of high-performance 3-1 interlock collapsing ALUs},
  author={James E. Phillips and Stamatis Vassiliadis},
  journal={IBM Journal of Research and Development},
A 32-bit 3-1 interlock coilapsing ALU, proposed to ailow the execution of two interioclced ALU-type instructions in one machine cycle using an instruction-level parallel machine implementation, is shown to produce results equivalent to a serial execution of the instructions using a 2-1 ALU. The equivalence is shown by deriving tables which represent all possible requirements for the serial execution of the instructions followed by the generalization of the table to represent sets of… CONTINUE READING

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