Profile-guided microarchitectural floor planning for deep submicron processor design

@article{Ekpanyapong2004ProfileguidedMF,
  title={Profile-guided microarchitectural floor planning for deep submicron processor design},
  author={Mongkol Ekpanyapong and Jacob R. Minz and Thaisiri Watewai and Hsien-Hsin S. Lee and Sung Kyu Lim},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2004},
  volume={25},
  pages={1289-1300}
}
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying the performance scalability substantially. An effective floorplanning algorithm can no longer ignore the information of dynamic communication patterns of applications. In this paper, using the profile information acquired at the architecture/microarchitecture level, we propose a… CONTINUE READING
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