Processor virtualization and split compilation for heterogeneous multicore embedded systems

@article{Cohen2010ProcessorVA,
  title={Processor virtualization and split compilation for heterogeneous multicore embedded systems},
  author={Albert Cohen and Erven Rohou},
  journal={Design Automation Conference},
  year={2010},
  pages={102-107}
}
Embedded multiprocessors have always been heterogeneous, driven by the power-efficiency and compute-density of hardware specialization. We aim to achieve portability and sustained performance of complete applications, leveraging diverse programmable cores. We combine instruction-set virtualization with just-in-time compilation, compiling C, C++ and managed languages to a target-independent intermediate language, maximizing the information flow between compilation steps in a split optimization… 
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References

SHOWING 1-10 OF 58 REFERENCES

A parallel dynamic compiler for CIL bytecode

This work proposes an approach that leverages on CMP features to expose a novel pipeline synchronization model for the internal threads of the dynamic compiler, ILDJIT, and is able to achieve significant speedups with respect to the baseline, when the underlying hardware exposes at least two cores.

Split Compilation: an Application to Just-in-Time Vectorization

This work focuses on automatic vectorization, a key optimization playing an increasing role in modern, power-efficient architectures, through a semantically rich and performance-friendly intermediate format.

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

A functional modelingstyle to capture data-intensive and control-dependent target applications, and a system architecture modeling style to seamlessly transform the functional model into the target architecture are proposed using Simulink.

The java hotspot TM server compiler

The Java HotSpotTM Server Compiler achieves improved asymptotic performance through a combination of object-oriented and classical-compiler optimizations. Aggressive inlining using class-hierarchy…

An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems

An experimental framework based on GCC is presented that validates the choice of CLI as a suitable processor-independent deployment format and offers a full development flow for the C language, generating a subset of pure CLI that does not require any virtual machine support other than a JIT compiler.

On the complexity of spill everywhere under SSA form

This paper provides an exhaustive study of the complexity of the "spill everywhere" problem in the context of the SSA form and identifies some polynomial cases but that are impractical in JIT context that can give hints to simplify formulations for the design of aggressive allocators.

Portable and Efficient Auto-vectorized Bytecode: a Look at the Interaction between Static and JIT Compilers

It is shown that vectorized bytecode is a viable approach that can deliver portable performance in the presence of SIMD extensions, while incurring only minor penalty when SIMD is not supported, and vectorization capabilities are added to the CLI port of the GCC compiler.

Split Register Allocation: Linear Complexity Without the Performance Penalty

A split register allocator is described showing that linear complexity does not imply reduced code quality, and a split compiler design is presented, where more expensive ahead-of-time analyses guide lightweight just-in-time optimizations.

Comparing the size of .NET applications with native code

  • Roberto CostaErven Rohou
  • Computer Science
    2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05)
  • 2005
The paper shows that the assumption of an impressive code size reduction is not reachable and it suggests that the adoption of such languages in embedded contexts be justified by additional arguments.

Trace-based just-in-time type specialization for dynamic languages

This work presents an alternative compilation technique for dynamically-typed languages that identifies frequently executed loop traces at run-time and then generates machine code on the fly that is specialized for the actual dynamic types occurring on each path through the loop.
...