Process optimization of lead-free wafer-level underfill material used in chip scale packaging

@article{Liu2005ProcessOO,
  title={Process optimization of lead-free wafer-level underfill material used in chip scale packaging},
  author={Yayun Liu and Gupta Umesh Dutt and A. Xiao},
  journal={Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.},
  year={2005},
  pages={293-297}
}
Wafer-level underfilling is an emerging technology that consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process enable the chip manufacturers to perform underfill at the wafer-level, thereby eliminating multiple steps in the packaging process and cutting production cost significantly. However, lead-free solder poses significant challenge to this new technology. Compared to eutectic solder, lead-free solder tends… CONTINUE READING

Citations

Publications citing this paper.
Showing 1-2 of 2 extracted citations

References

Publications referenced by this paper.

Novel lead-free wafer-level underfill materials for chip-scale packaging

G.Dutt, Y.Liu, A. Xiao
International Wafer-Level Packaging Congress, San Jose, CA, 2004. • 2004
View 1 Excerpt

Similar Papers

Loading similar papers…