Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

@article{Yelamarthi2008ProcessVA,
  title={Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic},
  author={Kumar Yelamarthi and Chien-In Henry Chen},
  journal={9th International Symposium on Quality Electronic Design (isqed 2008)},
  year={2008},
  pages={143-147}
}
A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay… CONTINUE READING