Multi-level Processing to Reduce Cost of Synchronization
- Nagi N. Mekhiel
- 2015 IEEE 17th International Conference on High…
In this paper, we present a novel process synchronization mechanism and the application of on-chip memories for process synchronization in multi-core systems. The multi-core processor architecture and a signaling scheme which supports the novel process synchronization mechanism are presented. The validity of the proposed synchronization mechanism is demonstrated by experiments on a virtual prototyping platform. Also, comparison against external memory based schemes shows that the proposed use of on-chip memories in multi-core process synchronization is an effective solution to reduce synchronization overheads, especially as the number of processor cores increase.