Process Synchronization in Multi-core Systems Using On-Chip Memories


In this paper, we present a novel process synchronization mechanism and the application of on-chip memories for process synchronization in multi-core systems. The multi-core processor architecture and a signaling scheme which supports the novel process synchronization mechanism are presented. The validity of the proposed synchronization mechanism is demonstrated by experiments on a virtual prototyping platform. Also, comparison against external memory based schemes shows that the proposed use of on-chip memories in multi-core process synchronization is an effective solution to reduce synchronization overheads, especially as the number of processor cores increase.

DOI: 10.1109/VLSID.2014.43

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@article{Joseph2014ProcessSI, title={Process Synchronization in Multi-core Systems Using On-Chip Memories}, author={Arun Joseph and Nagu R. Dhanwada}, journal={2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems}, year={2014}, pages={210-215} }