Process Optimization of Radiation-Hardened CMOS Integrated Circuits

@article{Derbenwick1975ProcessOO,
  title={Process Optimization of Radiation-Hardened CMOS Integrated Circuits},
  author={G. F. Derbenwick and B. L. Gregory},
  journal={IEEE Transactions on Nuclear Science},
  year={1975},
  volume={22},
  pages={2151-2156}
}
The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that… CONTINUE READING