Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement

@article{Blyzniuk2001ProbabilisticAO,
  title={Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement},
  author={Mykola Blyzniuk and Irena Kazymyra and Wieslaw Kuzmicz and Witold A. Pleskacz and Jaan Raik and Raimund Ubar},
  journal={Microelectronics Reliability},
  year={2001},
  volume={41},
  pages={2023-2040}
}
A new methodology of probabilistic analysis of CMOS physical defects in complex gates for the defect-based test is proposed. It is based on the developed approach for the identi®cation and estimation of the probability of actual faulty functions resulting from shorts caused by spot defects in conductive layers of IC layout. The aim of this methodology is realistic representation of physical defects in fault models. The list of defects, identi®ed faulty functions, defect coverage table… CONTINUE READING
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