Preprocessing Steiner problems from VLSI layout


VLSI layout applications yield instances of the Steiner tree problem over grid graphs with holes, which are considered hard to be solved by current methods. In particular, preprocessing techniques developed for Steiner problems over general graphs are not likely to reduce signiicantly such VLSI instances. We propose a new preprocessing procedure, combining earlier ideas from the literature to make them eeective for VLSI problems. Testing this procedure over the 116 instances of the SteinLib, we obtained signiicant reductions within reasonable computational times. These reductions allowed a branch-and-cut to solve 28 out of 32 open instances of the SteinLib, some with more than 10,000 vertices and 20,000 edges.

DOI: 10.1002/net.10035

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@article{Uchoa2002PreprocessingSP, title={Preprocessing Steiner problems from VLSI layout}, author={Eduardo Uchoa and Marcus Poggi de Arag{\~a}o and Celso C. Ribeiro}, journal={Networks}, year={2002}, volume={40}, pages={38-50} }