Preface i


This thesis describes the research which I conducted during my three year employment at the Institute for Experimental Mathematics. I hope that the work presented here can help serve as an example of one the institute's major goals, which is the enhancement of interdisciplinary work between engineers and mathematicians. Members of the Algebra and Number Theory Group, and the stimulating character of the Institute, contributed a great deal to the successful completion of the thesis. I wish to thank the following people from the institute, and from outside, for their support. First of all, I am indebted to my advisor, Prof. Han Vinck, for his support and advice through all stages of the project, and the outstanding work atmosphere he has created in our group. I am grateful to Prof. Richard Blahut from the University of Illinois and Prof. Henk van Tilborg from the Eindhoven University of Technology for their support as members of my Ph.D. committee. From the two math groups I would particularly like to thank Dr. van Wijngaarden for their general support and for being such pleasant coworkers. In particular, thanks to Olaf for the fruitful work we did jointly. Thanks also to Niko Lange from the Institute for Applied Microelectronics, Braun-schweig, for his help in evaluation issues regarding chip implementation. My thanks go also to Prof. Wayne Burleson and Jeong Yongijn from the University of Massachusetts at Amherst, for their hospitality and the insight in modern VLSI design methods. There are also several students I would like to thank. posed numerous interesting technical questions and helped me stay in touch with implementational issues. Last, but not least, I wish to thank Sarah Fowler for correcting my English, a task which certainly belonged to the less enjoyable ones needed for the completion of this thesis. ii Abstract This thesis describes various eecient architectures for computation in Galois elds of the type GF(2 k). \EEcient" refers to the fact that the architectures require a small number of elementary gates that are logical AND and exclusive OR. It is expected that, as a consequence, VLSI implementations of the architectures lead to chip designs which consume less area. All architectures are bit parallel, i.e. they apply only combinatorial logic and do not contain registers. This results in naturally fast architectures. The work focuses on the basic operations: multiplication, constant multiplication, and inversion. The architectures are based on algorithms which make …

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@inproceedings{Happle2008PrefaceI, title={Preface i}, author={Wolfgang Happle and Knn Reinhard and Hans-Georg R Orr and Volker Braun and Olaf Hooijen and Tamm and Horvv Ath and Karin Rufaut and Trung Van and Heiner Tran and Adriaan Schwarte and Paul Even and Leon Grutters and Bart Jansen and Roel Pouls and Tonny Teunesen and Volker Wittelsberger}, year={2008} }