Predictive modeling of capacitance and resistance in gate-all-around cylindrical nanowire MOSFETs for parasitic design optimization

Abstract

This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that C<inf>side</inf>, C<inf>of</inf>, R<inf>sd</inf>, R<inf>Q</inf> are dominant factors and should be treated as a major design concern. Among all the parameters, L<inf>sd</inf>, T<inf>g</inf> and N<inf>dop</inf> are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.

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Cite this paper

@article{Xu2010PredictiveMO, title={Predictive modeling of capacitance and resistance in gate-all-around cylindrical nanowire MOSFETs for parasitic design optimization}, author={Qiumin Xu and Jibin Zou and Jieyin Luo and Runsheng Wang and Ru Huang}, journal={2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology}, year={2010}, pages={1958-1960} }