K. Suenaga, S. Bota, R. Picos, E. Isern, M. Roca, E. Garcia-Moreno Electronic Technology Group, Physics Department University of Balearic Islands Palma de Mallorca, 07122. SPAIN Tel: +34-971-259-569 Fax: +34-971-173-426 e-mail : firstname.lastname@example.org Abstract In this paper, a sequential test technique is proposed to test a RF front-end receiver. With this technique the test circuitry can be reused by the receiver building blocks. The method is suitable to be fully integrated On-Chip. Moreover, the test area overhead has been kept low by using the receiver LO in the test circuitry. Therefore the test circuitry required to generate the test stimuli are an IF generator and an auxiliary mixer. The above technique has been combined with a test strategy based on the estimation of selected performance parameters of the receiver building blocks. These estimations are done by using easily measurable test observables as DC supply current consumption. RMS estimation errors for the gain and the 1dB compression point of the LNA and the down converter in the receiver chain are all below 2 %.