Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

@article{Matsutani2011PredictionRA,
  title={Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors},
  author={Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano and Tsutomu Yoshinaga},
  journal={IEEE Transactions on Computers},
  year={2011},
  volume={60},
  pages={783-799}
}
Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a low-latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce communication latency. The packets coming into the prediction routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits… CONTINUE READING
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