Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Abstract

Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a low-latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce communication latency. The packets… (More)
DOI: 10.1109/TC.2011.17

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