# Predicting the Phase Noise of PLL-Based Frequency Synthesizers

@inproceedings{Kundert2001PredictingTP, title={Predicting the Phase Noise of PLL-Based Frequency Synthesizers}, author={Kenneth S. Kundert}, year={2001} }

A methodology is presented for predicting the phase noise of a PLL-based frequency synthesizer using simulation that is both accurate and efficient. The methodology begins by characterizing the phase noise behavior of the blocks that make up the PLL using transistor-level RF noise simulation. For each block, the phase noise is extracted and applied to a phase-domain model for the entire PLL.

## 14 Citations

### Frequency Synthesis Modeling Jitter in PLL-based Frequency Synthesizers

- Computer Science
- 2001

A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that is both accurate and efficient and efficient enough to be applied to PLLs acting as frequency synthesizers with large divide ratios.

### Modeling Jitter in PLL-based Frequency Synthesizers

- Computer Science
- 2001

A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that is both accurate and efficient and efficient enough to be applied to PLLs acting as frequency synthesizers with large divide ratios.

### Predicting the jitter of PLL-DLL Based frequency synthesizers

- Computer ScienceInt. J. Wavelets Multiresolution Inf. Process.
- 2014

Jitter of PLL and DLL has been reduced by proposed technique and the methodological nature of the approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same.

### A reference spur estimation method for integer-N PLLs

- Engineering2013 IEEE 10th International Conference on ASIC
- 2013

In this paper, the spur transfer function is derived, and the method is implemented in Verilog-A, where the prediction results match well with the close-loop transistor-level simulation.

### A band-reject nested-PLL phase-noise reduction scheme for clock-cleaners

- Engineering2011 IEEE International Symposium of Circuits and Systems (ISCAS)
- 2011

This paper proposes a clock-conditioner architecture that minimizes the incidence of the input signal phase-noise (PN) in phase-locked-loop (PLL)-based cleaners by modifying the corresponding…

### A Band-Reject Nested-PLL Clock Cleaner Using a Tunable MEMS Oscillator

- EngineeringIEEE Transactions on Circuits and Systems I: Regular Papers
- 2014

To maintain lower integrated phase noise, the proposed scheme uses a high- Q MEMS-based VCO to effectively smoothen the transition of the response between the two dominant noise sources.

### Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise

- EngineeringASP-DAC
- 2005

The proposed ionlinear technique captum the dynamics of complex phenomena such as locking, cycle slipping and power supply noise induced PLL jitter, replicating qualitative features from full SPICE simulations accurately while providing speedups of over two orders of magnitude.

### An ultra-low phase-noise ka-band tunable frequency synthesizer

- Physics2008 IEEE International Frequency Control Symposium
- 2008

This paper presents a Ka-band, fractional-N phase-locked loop (PLL) for use in radar applications. The PLL, with a tuning range of 31.7-36.0 GHz, utilizes a high-speed sigma-delta SigmaDelta…

### Feasability study of frequency doubling using a dual-edge method

- Engineering
- 2010

The performance of integrated Frequency Synthesizers relies on a clean fixed reference frequency, which is usually derived from a crystal. Unfortunately, commercially cheap crystal oscillators are…

### Feasibility study of frequency doubling using an anxor-gate method

- Physics, Engineering
- 2013

The performance of the integrated Frequency Synthesizers relies on a clean fixed reference frequency, which is usually derived from a crystal. Unfortunately, commercial low cost crystal oscillators…

## References

SHOWING 1-10 OF 33 REFERENCES

### Modeling Jitter in PLL-based Frequency Synthesizers

- Computer Science
- 2001

A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that is both accurate and efficient and efficient enough to be applied to PLLs acting as frequency synthesizers with large divide ratios.

### Modeling and Simulation of Jitter in Phase-Locked Loops

- Computer Science
- 1997

A methodology is presented for predicting the jitter performance of a PLL using simulation that is both accurate and efficient, and efficient enough to be applied to complex systems, such as frequency synthesizers with large divide ratios or fractional-N synthesizers.

### Simulation and modeling of phase noise in open-loop oscillators

- Physics, EngineeringProceedings of Custom Integrated Circuits Conference
- 1996

This paper presents a discussion about the definition of phase noise for general oscillation waveforms; a numerical method for transistor-level simulation and characterization of phase noise in…

### Delta-sigma modulation in fractional-N frequency synthesis

- Physics
- 1993

A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL).…

### Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems

- Physics
- 1997

Noise in Free Running Oscillators: Behavioral Modeling and Simulation of Phase-Locked Loops, and Conclusions and Future Work.

### Behavioral simulation techniques for phase/delay-locked systems

- PhysicsProceedings of IEEE Custom Integrated Circuits Conference - CICC '94
- 1994

Simulation techniques are described in the framework of phase/delay-locked systems, but simulation methodology and the results attained in this work are applicable to the behavioral simulation of mixed-mode nonlinear dynamic systems.

### Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise

- Computer ScienceProceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
- 2000

The origins and characteristics of cyclostationary noise are described in a way that allows designers to understand the impact ofcyclostationarity on their circuits.

### Physical processes of phase noise in differential LC oscillators

- PhysicsProceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
- 2000

There is an unprecedented interest among circuit designers today to obtain insight into the mechanisms of phase noise in LC oscillators. For only with this insight is it possible to optimize…

### Modeling and Simulation of Jitter in PLL Frequency Synthesizers

- Engineering
- 2001

A selection of photos from the 2016/17 USGS report on quantitative hazard assessments of earthquake-triggered landsliding and liquefaction, released on 5 May 2016.

### Determination of the correlation spectrum of oscillators with low noise

- Physics
- 1989

A general expression for the correlation spectrum of an oscillator, described by a set of nonlinear ordinary differential equations with intrinsic noise sources, is derived by a first-order…