• Corpus ID: 8259821

Predicting the Phase Noise of PLL-Based Frequency Synthesizers

@inproceedings{Kundert2001PredictingTP,
  title={Predicting the Phase Noise of PLL-Based Frequency Synthesizers},
  author={Kenneth S. Kundert},
  year={2001}
}
A methodology is presented for predicting the phase noise of a PLL-based frequency synthesizer using simulation that is both accurate and efficient. The methodology begins by characterizing the phase noise behavior of the blocks that make up the PLL using transistor-level RF noise simulation. For each block, the phase noise is extracted and applied to a phase-domain model for the entire PLL. 

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References

SHOWING 1-10 OF 33 REFERENCES

Modeling Jitter in PLL-based Frequency Synthesizers

TLDR
A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that is both accurate and efficient and efficient enough to be applied to PLLs acting as frequency synthesizers with large divide ratios.

Modeling and Simulation of Jitter in Phase-Locked Loops

TLDR
A methodology is presented for predicting the jitter performance of a PLL using simulation that is both accurate and efficient, and efficient enough to be applied to complex systems, such as frequency synthesizers with large divide ratios or fractional-N synthesizers.

Simulation and modeling of phase noise in open-loop oscillators

This paper presents a discussion about the definition of phase noise for general oscillation waveforms; a numerical method for transistor-level simulation and characterization of phase noise in

Delta-sigma modulation in fractional-N frequency synthesis

A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL).

Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems

TLDR
Noise in Free Running Oscillators: Behavioral Modeling and Simulation of Phase-Locked Loops, and Conclusions and Future Work.

Behavioral simulation techniques for phase/delay-locked systems

TLDR
Simulation techniques are described in the framework of phase/delay-locked systems, but simulation methodology and the results attained in this work are applicable to the behavioral simulation of mixed-mode nonlinear dynamic systems.

Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise

  • J. PhillipsK. Kundert
  • Computer Science
    Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
  • 2000
TLDR
The origins and characteristics of cyclostationary noise are described in a way that allows designers to understand the impact ofcyclostationarity on their circuits.

Physical processes of phase noise in differential LC oscillators

  • J. RaelA. Abidi
  • Physics
    Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
  • 2000
There is an unprecedented interest among circuit designers today to obtain insight into the mechanisms of phase noise in LC oscillators. For only with this insight is it possible to optimize

Modeling and Simulation of Jitter in PLL Frequency Synthesizers

TLDR
A selection of photos from the 2016/17 USGS report on quantitative hazard assessments of earthquake-triggered landsliding and liquefaction, released on 5 May 2016.

Determination of the correlation spectrum of oscillators with low noise

A general expression for the correlation spectrum of an oscillator, described by a set of nonlinear ordinary differential equations with intrinsic noise sources, is derived by a first-order