Predicting the Impact of Implementation Level Aspects on Parallel Application Performance


SP (series-parallel) programming models show well known advantages when program structure, cost estimation and scheduling are an issue. Transforming a parallel computation which DAG is NSP into its SP equivalent under the restricted SP synchronization framework could lead to a loss of efficiency. Nevertheless, it has been recently shown that this loss is often limited to tens of percents, which makes SP programming still a good alternative. In that previous research, we introduced an analytic cost model which allowed us to predict the effects of DAG topology on the execution time of a computation when applied at the programming level. In this work, we describe how this cost modeling approach can also be taken to the implementation level in order to explain or even predict the sometimes surprising effects on performance, caused by mapping decisions and language or implementation details. The application of this new approach to predict various performance effects on real applications showing both restricted and non-restricted synchronization structures is also shown in this paper.

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@inproceedings{GonzlezEscribano2001PredictingTI, title={Predicting the Impact of Implementation Level Aspects on Parallel Application Performance}, author={Arturo Gonz{\'a}lez-Escribano and Arjan J. C. van Gemund and Valentı́n Carde{\~n}oso-Payo and Miguel Delibes}, year={2001} }