PreSET: Improving performance of phase change memories by exploiting asymmetry in write times

@article{Qureshi2012PreSETIP,
  title={PreSET: Improving performance of phase change memories by exploiting asymmetry in write times},
  author={Moinuddin K. Qureshi and Michele Franceschini and Ashish Jagmohan and Luis Alfonso Lastras-Monta{\~n}o},
  journal={2012 39th Annual International Symposium on Computer Architecture (ISCA)},
  year={2012},
  pages={380-391}
}
Phase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read requests. For our baseline PCM system, the slow writes increase the effective read latency by almost 2X, causing significant performance degradation. This paper alleviates the problem of slow writes by exploiting the fundamental property of PCM… CONTINUE READING
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