Practical Bounded-Skew Clock Routing

  title={Practical Bounded-Skew Clock Routing},
  author={Andrew B. Kahng and Chung-Wen Albert Tsao},
  journal={VLSI Signal Processing},
In Clock routing research, such practical considerations as hierarchical buffering, rise-time and overshoot constraints, obstacleand legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing for varying… CONTINUE READING


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Showing 1-10 of 23 references

Pillage, “Skew and delay optimization for reliable buffered clock trees,

  • S. Pullela, N. Menezes, J. Omar, L.T
  • in Proc. IEEE Intl. Conf. Computer-Aided Design…
  • 1993
Highly Influential
5 Excerpts

Visibilitypolygon search and euclidean shortest paths,

  • T. Asano, L. Guibas, J. Hershberger, H. Imai
  • PMR Journal of VLSI Signal Processing 08-Kahng…
  • 1997
1 Excerpt

VLSI Clock Net Routing,

  • C.-W.A. Tsao
  • Ph.D. thesis,
  • 1996
1 Excerpt

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