Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs

@inproceedings{Benini2001PoweringNO,
  title={Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs},
  author={Luca Benini and Giovanni De Micheli},
  booktitle={ISSS},
  year={2001}
}
We consider systems on chips (SoCs) that will be designed and produced in five to ten years from today, with gate lengths in the range 50-100nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology. Specifically, we consider energy consumption reduction… CONTINUE READING

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