PowerDepot: Integrating IP-based power modeling with ESL power analysis for multi-core SoC designs

@article{Hsu2011PowerDepotII,
  title={PowerDepot: Integrating IP-based power modeling with ESL power analysis for multi-core SoC designs},
  author={Chen-Wei Hsu and Jia-Lu Liao and Shan-Chien Fang and Chia-Chien Weng and Shi-Yu Huang and Wen-Tsan Hsieh and Jen-Chieh Yeh},
  journal={2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)},
  year={2011},
  pages={47-52}
}
In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile the power consumption of a multi-core SoC running a complete application while retaining high… CONTINUE READING
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