Power-scan chain: design for analog testability

Abstract

This paper reports a Design for Testability technique, which provides necessary diagnostic capability for signature-based testing of analog circuits. To facilitate this kind of testing, it is preferable to observe the current (or voltage) signatures of individual cores instead of observing the current (or voltage) signature of the whole analog SoC. Therefore, our DfT works like a power-scan chain aimed at turning on/off analog cores in an individual manner, providing an observability means at the core’s power and output terminals, and at exciting the core under test. The proposed DfT can be used for engineering precharacterization as well, and can easily be interfaced to standards like IC and IEEE 1149.1 TAP controllers. In this paper we further provide experimental evidence of our approach as applied to an RF device.

DOI: 10.1109/TEST.2005.1583963

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Cite this paper

@inproceedings{Zjajo2005PowerscanCD, title={Power-scan chain: design for analog testability}, author={Amir Zjajo and Hendrik J. Bergveld and Rodger Schuttert and Jos{\'e} Pineda de Gyvez}, booktitle={ITC}, year={2005} }