Power optimization in current mode circuits


We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit. Power reduction is achieved through turning off the redundant comparator circuits using a switch-architecture… (More)
DOI: 10.1109/ICVD.2005.139

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