Power-efficient time-to-digital converter for all-digital frequency locked loops

Abstract

An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops is presented. The selected architecture uses a Vernier delay line where the commonly used D flip-flops are replaced with a single enable transistor in the delay elements. This architecture allows for an area efficient and power efficient implementation. The dynamic range of the… (More)
DOI: 10.1109/ECCTD.2015.7300008

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