• Corpus ID: 108806867

Power efficient design of SRAM arrays and optimal design of signal and power distribution networks in VLSI circuits

  title={Power efficient design of SRAM arrays and optimal design of signal and power distribution networks in VLSI circuits},
  author={Behnam Amelifard},

Comparative Performance Analysis of Different Flip Flop Configurations

------------------------------------------------------------------***-------------------------------------------------------------------Abstract Computer performance is increasingly limited by the

Salvaging chips with caches beyond repair

The limits of the traditional spares-based defect-tolerance approaches for SRAMs are shown, a software-based approach is proposed and implemented, and it is demonstrated that this approach can significantly increase microprocessor chip yields compared to the traditional approaches and dramatically increases effective computing capacity.

Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths

The problem of low-power fanout optimization can be reduced to inverter-chain optimization problem and the minimization of the total power consumption of an inverter chain as a geometric program is formulates.

Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips

It is shown that, in a SoC design with static-voltage assignment, a multilevel tree topology of suitably chosen dc-dc converters between the power source and loads can result in higher power efficiency in the PDN.



A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique.

A fanout optimization algorithm based on the effort delay model

Experimental results show that compared with previous approaches, both for continuous and discrete buffer libraries, LEOPARD achieves a significant reduction in the total buffer area subject to the required time constraints.

SRAM leakage suppression by minimizing standby supply voltage

This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing, and forms the basis for further design space explorations.

An effective power mode transition technique in MTCMOS circuits

Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a one to two orders of magnitude improvement in the product of the maximum ground current and the wake up time.

TPS60503 Datasheet

  • [online] http://www.ti.com/lit/gpn/tps60503

Impact of CMOS technology scaling on the atmospheric neutron soft error rate

If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L/sub G/.

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption

Analysis and future trend of short-circuit power

  • K. NoseT. Sakurai
  • Engineering
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • 2000
A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the

Gate oxide leakage current analysis and reduction for VLSI circuits

A fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/), and proposes the use of pin reordering as a means to reduce I/ sub gate/.

Leakage in nano-scale technologies: mechanisms, impact and design considerations

Various intrinsic leakage mechanisms including weak inversion, gateoxide tunneling and junction leakage etc are explored, including process variation compensating techniques to reduce delay and leakage spread, while meeting power constraint and yield.