Power dissipation issues in interconnect performance optimization for sub-180 nm designs

@article{Banerjee2002PowerDI,
  title={Power dissipation issues in interconnect performance optimization for sub-180 nm designs},
  author={Kaustav Banerjee and Amit Mehrotra},
  journal={2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)},
  year={2002},
  pages={12-15}
}
This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and inter-buffer interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the… CONTINUE READING

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