Power comparison of an asynchronous and synchronous network on chip router

  title={Power comparison of an asynchronous and synchronous network on chip router},
  author={Pooria M. Yaghini and Ashkan Eghbal and Seyyed Amir Asghari and Hossein Pedram},
  journal={2009 14th International CSI Computer Conference},
This paper presents an asynchronous and a synchronous NoC router architecture. The asynchronous scheme is implemented by the help of CSP-Verilog language and the synchronous one is designed employing VHDL language. Their designs are similar except the extra links which are in charge of handshaking processes in asynchronous architecture. According to the experimental results the transition counts of buffer, and switch components in synchronous router are almost 82% and 60% of asynchronous one… CONTINUE READING


Publications referenced by this paper.
Showing 1-10 of 10 references

Chatha, " Qualityof-Service and Error Control Techniques for Networkon-Chip Architectures

  • P. Vellanki, N. Banerjee, K.S
  • Proceedings of the 14th ACM Proceedings of the…
  • 2004
1 Excerpt

Chatha, "A Power and Performance Model for Network-on-Chip Architectures

  • N. Banerjee, P. Vellanki, K.S
  • Proceedings on Design, Automation and Test in…
  • 2004
1 Excerpt

Pinkston, "A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns

  • Wai Hong Ho, T.M
  • Proceedings of International Symposium on High…
  • 2003
1 Excerpt

Similar Papers

Loading similar papers…